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AR# 63457

2014.4 Vivado Power - Why is the timing performance reduced when BRAM power optimization is enabled?


 Why is the timing performance reduced when block RAM power optimization is enabled?


If bram power-opt is performed in a pre-place state, the power-opt engine has limited/imprecise timing information.

As a result, timing performance may degrade due to the injected clock gating logics.

If this is an issue, we suggested performing bram power-opt in a post-place state.

In this state the power-opt engine will use more accurate timing information to reject changes that may lead to potential timing degradations. 

The following is an example script:

opt_design -retarget -propconst -sweep -remap -resynth_area -resynth_seq_area # w/o bram power-opt 
opt_design # bram power-opt is performed after placement 
report_timing_summary -file timing_design_pwr_opt_pwropt.rpt

AR# 63457
Date Created 01/29/2015
Last Updated 01/29/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4