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AR# 63464

Vivado - How can I check to see if there is a gated clock in my design?

Description

 How can I check to see if there is a gated clock in my design?

Solution

You can use the following DRC check command:

report_drc -check PLHOLDVIO-2 

Example DRC result:

PLHOLDVIO-2#1 Warning

Non-Optimal connections which could lead to hold violations  

A LUT data_1[3]_i_1 is driving clock pin of 21 cells. This could lead to large hold time violations. First few involved cells are:

    data_1_reg[3] {FDRE}

    data_4_reg[3]_data_2_reg_r_2 {FDRE}

....

AR# 63464
Date Created 01/29/2015
Last Updated 03/26/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite