Does LwIP support all PHYs using the CONFIG_LINKSPEED_AUTODETECT BSP/LwIP setting?
A design with Micrel PHY set to 1Gb/s or 100Mb/s only shows 10Mb/s in the UART output when the SDK LwIP Echo SW application is run:
-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
link speed: 10
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
TCP echo server started @ port 7
All PHYs are not supported.
To use a PHY other than the Marvell PHY please follow these steps:
The following is the basic flow
followed in the LwIP for autonegotiation mode.
- Detect the PHY address.
Generally poll the register 2 (PHY identifier 1) and 3 (PHY identifier 2) for
each possible PHY address (0 to 31).
On seeing valid entries (non FF) for a PHY
address register the detected PHY address.
- For the PHY address
detected, write to register 2, Control Register MAC (page 2) to set proper
RGMII Rx and Tx timing control bits.
For the PHY address detected,
configure the register 4 (autoneg copper advertisement reg) for 100 and 10 Mbps
for relevant values.
You can also configure fields like asymmetric pause and
pause in this register.
- For the PHY address
detected, configure the register 9 (1000 BaseT control register) to advertise
1000 Mbps (if gigabit mode is to be supported).
Enable autonegotiation in
register 0 (control reg) and restart autoneg through register 0 (control reg).
Wait till autoneg is over
by reading register 1 (status register).
Once autoneg is over, read
the copper specific status register (register 17, page 0 for Marvell PHY 88E1116R)
to know about the negotiated speed and duplex.
Until autoneg is complete,
periodically read an error status register (for Marvell PHY 88E1116R, it is
register page 0, register 19, copper specific status register 2) to notify
autoneg of errors if any.
Please note that the above is
the flow that Xilinx implements assuming Marvell PHYs.
As per IEEE 802.3 standards, the
first 15 registers are the standard registers that each PHY vendor must
Anything beyond that is vendor
If you are using PHY other than
Marvell, examine their specifications and find the corresponding register definitions, then update the code accordingly.