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AR# 63542

Vivado Partial Reconfiguration -CRITICAL WARNING: [Drc 23-20] Rule violation (HDPR-51) Clock Net Rule Violation

Description

In my design, the 2 clock ports of a reconfigurable cell share the same global clock driver in static logic.

This causes the following warning message:
 

CRITICAL WARNING: [Drc 23-20] Rule violation (HDPR-51) Clock Net Rule Violation - Reconfigurable cell 'U1' has multiple ports ' clk2 clk1 ' sharing the same clock driver.
The connection is not efficient for clock resource usage and also may cause extra skew in timing evaluation.
It is recommended to use 1 port per clock driver


Can I ignore this message safely?
 

Solution

When 2 clock ports of a reconfigurable cell share the same global clock driver in the static logic, it means that even if in the same clock region, 2 different BUFHs will be used for these 2 clocks.

The common clock path of 2 clocks will be shortened, which will reduce the clock pessimism value and have negative impact on the paths between 2 clocks in the same clock region.

If there is no timing violation in the timing report, this critical warning can be ignored safely.
AR# 63542
Date Created 02/10/2015
Last Updated 02/24/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite