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AR# 63564

2014.x Vivado IP Flows - In non-project mode my VHDL IP core is being generated as a Verilog IP, why?

Description

I have some XCI files which I have saved in revision control. 

When I read, (read_ip) these IPs into memory, (non-project flow) and then try to generate them using the "generate_target" command, I notice my VHDL IP cores are being generated as Verilog cores.

See the following script example:

create_project -in_memory -part xc7vx415tffg1158-2
read_ip ./local_pcs_pma/local_pcs_pma.xci
generate_target all [get_files ./local_pcs_pma/local_pcs_pma.xci]

In my original XCI file which was read into the project, the PREFHDL setting was VHDL

                <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>

But after running the IP generation, it then changes to Verilog.

                <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">Verilog</spirit:configurableElementValue>

This causes issues with the constraints for my project as instance names no longer match.

Is this expected behavior, and is it possible to ensure that VHDL is maintained?



Solution

This issue has been seen in Vivado 2014.x and is expected to be fixed in a future release of Vivado.

A work-around is to add the following command into the script prior to generating the IPs.
 
This command is at the project level and works for all IPs.

set_property target_language VHDL [current_project]

So the above script becomes:
 

create_project -in_memory -part xc7vx415tffg1158-2
read_ip ./local_pcs_pma/local_pcs_pma.xci
set_property target_language VHDL [current_project]
generate_target all [get_files ./local_pcs_pma/local_pcs_pma.xci]

AR# 63564
Date Created 02/13/2015
Last Updated 03/30/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4