In a partial reconfiguration design, the source and destination registers of a timing path across the boundary of static and dynamic logic are placed near each other, but the Partpin is far away.
In the above diagram, the green one is the source register in static logic.
The yellow one is the PartPin the timing path will pass.
The red one is the destination register in RM.
In the timing report for the placed design, the estimated net delay from Source register to Destination register is 0.277, which is reasonable in the non-PR design.
However, in the timing report for the routed design, the net delay from Source register to Destination register is 2.356, which is much larger than the estimated value.
The reason for the large difference is that the report_timing command does not consider the effect of Partpin when estimating the boundary net delay for the placed PR design.