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AR# 63599

Vivado 2015.1, IP Integrator - CRITICAL WARNING: [BD 41-1660] Reset pin /axi_interconnect_0/S00_ARESETN (associated clock /axi_interconnect_0/S00_ACLK) is connected to asynchronous reset source /ARESETN. This may prevent design from meeting timing

Description

What is the meaning of the following critical warning? 

How do I resolve it?

CRITICAL WARNING: [BD 41-1660] Reset pin /axi_interconnect_0/S00_ARESETN (associated clock /axi_interconnect_0/S00_ACLK) is connected to asynchronous reset source /ARESETN.
This may prevent design from meeting timing. Please update 'Associated Reset' configuration parameter of external clock-source /M_AXI_GP0_ACLK to include reset source name ARESETN.

Solution

This warning states that the external reset used in the block design has not been related to the clock of an interface that is using it. 

In other words, the block design must be told which clocks a reset is synchronous to.

To relate a reset to the clock, the ASSOCIATED_RESET parameter of a clock interface should be set to the external reset name. 

This can be performed in the GUI by double-clicking on the clock interface port, and setting the Associated Reset parameter.

Additional resets can be delimited by colons.

For example, to perform the change via TCL for a reset interface ARESETN to be related to clock interface M_AXI_GP0_ACLK , the following command can be used:

set_property CONFIG.ASSOCIATED_RESET ARESETN [get_bd_ports M_AXI_GP0_ACLK]
AR# 63599
Date Created 02/17/2015
Last Updated 04/30/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite