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AR# 63609

UltraScale and UltraScale+ Soft Error Mitigation Controller - Release Notes


This is the Release Note Answer Record for the Soft Error Mitigation Controller (SEM IP) for UltraScale FPGA and newer device families.

*** Important Note for SEM IP Designs ***

Beginning with the Vivado 2015.3 release, the SEM IP Product Guide contains an appendix containing the IP Design Checklist.

To aid with integrating SEM IP into a design, review the IP Design Checklist and ensure all recommendations are adhered to:

PG187 (UltraScale Architecture Soft Error Mitigation Controller v3.1)


Version Information:

Vivado Version IP Version
Vivado 2015.1

v2.0 rev2

Vivado 2015.3 v3.0 rev0
Vivado 2015.4v3.0 rev1
Vivado 2016.1v3.1 rev0
Vivado 2016.2v3.1 rev1
Vivado 2016.3v3.1 rev2

Supported Devices:

UltraScale FPGA:

The SEM IP supports all UltraScale FPGAs except the XCKU025. The XCKU025 has a reduced set of configuration features. Please refer to (DS890) and (UG570) for more information.

For the supported devices, SEM IP is a Production IP as of Vivado 2016.1.

UltraScale+ FPGA and Zynq UltraScale+ MPSoC devices:

Device IP Status Remark
Pre-ProductionHardware Validation Pending
Hardware Validation Pending
XCKU11PPre-ProductionHardware Validation Pending
XCKU15PPre-ProductionHardware Validation Pending
XCZU2Pre-ProductionHardware Validation Pending
XCZU3Pre-ProductionHardware Validation Pending
XCZU4Pre-ProductionHardware Validation Pending
XCZU5Pre-ProductionHardware Validation Pending
XCZU7Pre-ProductionHardware Validation Pending

*This table will be updated for each Vivado tools release, and lists the presently supported device under the most recent version.

**Contact Xilinx Technical Support for more information.

General Guidance

Answer RecordTitle

Applicable Version

(Xilinx Answer 67939)Soft Error Mitigation IP - Location of the makedata.tcl file changed since 2016.32016.3
(Xilinx Answer 66570)UltraScale Architecture Soft Error Mitigation Controller - Guidance for testing with error injection

(Xilinx Answer 67086)UltraScale - SEM IP - How to use the SEM IP error report to look up bit error locations using essential bit data in the EBD file?
(Xilinx Answer 67128)SEM support limitations for UltraScale+ ES1 devices
(Xilinx Answer 67180)Can SEM support clock frequencies lower than 8 MHz?
(Xilinx Answer 67178)Soft Error Mitigation (SEM) IP UltraScale and UltraScale+ Bitstream Encryption and Authentication 2016.1
(Xilinx Answer 67041)Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator
(Xilinx Answer 65402) Soft Error Mitigation (SEM) IP - Increased interface errors when performing error injection into configuration memory2015.1
(Xilinx Answer 64512) UltraScale SEM v2.0 device and feature support guidance for 2015.12015.1
(Xilinx Answer 65550) Soft Error Mitigation (SEM) IP SSI timing closure might not be met without pin LOCs2015.1
(Xilinx Answer 65551)UltraScale Soft Error Mitigation (SEM) IP XCVU440 makedata.tcl only supports monolithic die SPI flash devices 2016.1
(Xilinx Answer 67041)Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator2016.1

Known Issues

Answer Record Title Version Found

Version Resolved

(Xilinx Answer 64513) UltraScale SEM v2.0 Query by LFA command does not work for SSI devices2015.12015.3
(Xilinx Answer 65552) UltraScale Soft Error Mitigation (SEM) IP XCVU190 classification makedata.tcl is incorrect 2015.3


(Xilinx Answer 66906)Soft Error Mitigation (SEM) IP [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check2016.12016.3
(Xilinx Answer 66905)Soft Error Mitigation (SEM) IP SSI device status_heartbeat timing violation2016.12016.3

Note: The "version found" column lists the version the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Child Answer Records

AR# 63609
Date Created 02/18/2015
Last Updated 10/13/2016
Status Active
Type Release Notes
  • Virtex UltraScale
  • Virtex UltraScale+
  • Kintex UltraScale
  • More
  • Kintex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite
  • Soft Error Mitigation