We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63667

UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model


Version Found: DDR4 v7.0

Version Resolved: See (Xilinx Answer 69035)

I am simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model.

I am receiving the following error message:

VIOLATION: cmdWR BG:0 B:0 A:0 (BL:8 WL:11 RL:11) @4299688 Required: tRCD-AL - 1 clocks.


This violation occurs because of an issue with the Micron memory model using the wrong speed bin parameters.

Please use the most up to date memory model from Micron to resolve the issue.

Revision History:

04/01/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 63667
Date 01/02/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • More
  • Vivado Design Suite - 2015.4
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4.2
  • Less
  • MIG UltraScale
Page Bookmarked