UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63667

MIG UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model

Description

Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)

I am simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model.

I am receiving the following error message:
 

VIOLATION: cmdWR BG:0 B:0 A:0 (BL:8 WL:11 RL:11) @4299688 Required: tRCD-AL - 1 clocks.



Solution

This violation occurs because of an issue with the Micron memory model using the wrong speed bin parameters.

Please contact Micron for a solution and timeline for when this issue will be fixed.

Revision History:
04/01/2015 - Initial Release

Linked Answer Records

Master Answer Records

AR# 63667
Date Created 02/23/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale