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AR# 63667

MIG UltraScale DDR4 - VIOLATION: cmdWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model


Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)

I am simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model.

I am receiving the following error message:

VIOLATION: cmdWR BG:0 B:0 A:0 (BL:8 WL:11 RL:11) @4299688 Required: tRCD-AL - 1 clocks.


This violation occurs because of an issue with the Micron memory model using the wrong speed bin parameters.

Please contact Micron for a solution and timeline for when this issue will be fixed.

Revision History:
04/01/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 63667
Date 04/30/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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