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# AR# 63681

## Description

The Zynq DDRC Board Delay Calculation Table erroneously adds an extra 160ps/inch conversion factor.

This results in erroneous DQS to CLK Delay (ns) results.

## Solution

As a work-around, use the following calculation to manually calculate the DQS to CLK delay and use the 'User Input' option to input the results to the GUI.

********************************************************************************************************************************************************************
CLK Delay  =   (<CLK length in inch>  *  <CLK propagation Delay ps/inch>) +  <CLK Package Delay in ps>
DSQ Delay  =   (<DQS length in inch>  *  <DQS propagation Delay ps/inch>) +  <DQS Package Delay ps>

DQS to CLK delay = CLK Delay - DQS Delay
********************************************************************************************************************************************************************

For Example:

Taking the values for CLK0 and DQS0 length as equal to 1mm we can determine that this equals 0.039370 inches.

Using the propagation delay factor 160ps/inch we can then determine that 0.039370 * 160 = 6.2992ps

So CLK0 and DQS0 length is 6.2992ps.

Determining DQS to CLK delay, we add the length delay and the package delay for DQS0 and CLK0 and subtract these:

DQS0 = 68.4725 + 6.2992 = 74.7717
CLK0 = 61.0905 + 6.2992 = 67.3897

DQS to CLK delay is 67.3897 - 74.7717 = -7.382ps or -0.007ns rounded.

This issue is planned to be fixed starting in Vivado 2015.2.
AR# 63681
Date 03/11/2015
Status Active
Type General Article
Devices
• SoC
• Zynq-7000
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