Version Found: MIG UltraScale v6.1
Version Resolved: See (Xilinx Answer 58435)
During calibration, delays are added to DQ and QK signals which can move these signals away from their corresponding QVLD position.
Therefore, QVLD calibration is required to adjust the QVLD signals accordingly by incrementing or decrementing the IDELAY taps.
For MIG UltraScale RLDRAM3 designs, the IDELAY taps do not move which can cause data errors in hardware.
To determine if this is the root cause of data errors seen in your system, check that all of the "user_rd_valid" bits assert on the same clock cycle when 4 commands (BL2) or 2 command (BL4) are sent on the same "user_cmd" bus.
To fix the issue, the following code changes inside rld_riu_map.sv are required.
Open rld_riu_map.sv and find each instance of "qvld", then change the riu_addr_cal value based on the table below:
|if value equal to||change to|
This needs to be changed to:
02/24/2015 - Initial Release