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AR# 63714

2014.4 Partial Reconfiguration - False message "Reconfigurable Pblock crossing SLR using Global Clock resources" in HDPR-58 in a monolithic device


I have a partial reconfiguration design targeting a monolithic UltraScale device (the whole device is one SLR), but place_design fails with the following message mentioning "SLR":

ERROR: [DRC 23-20] Rule violation (HDPR-58) Reconfigurable Pblock crossing SLR using Global Clock resources cannot be in clock regions that contain non-reconfigurable sites - HD.RECONFIGURABLE Pblock '<name>' is not fully aligned on clock region '<name>'. 
A reconfigurable Pblock that ranges Global Clock sources must use either an entire clock region or none of it. 
Because this clock region contains CONFIG_SITE sites, the clock region must be removed from the range.

The message "Reconfigurable Pblock crossing SLR using Global Clock resources"  is incorrect for this design, since it is impossible to be cross-SLR in a monolithic device.
The statement about the clock region containing CONFIG_SITE is correct.



In Vivado 2015.1, the message for rule violation HDPR-58 is updated.

In the above situation, no message about SLR is issued and only a message about CONFIG_SITE is issued.

AR# 63714
Date 03/31/2015
Status Archive
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
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