In a partial reconfiguration design, there is no hold time violation after the 1st configuration.
After the 2nd configuration completes, some hold time violation occur in the interface paths. (WNS=-0.057)
All of the paths with hold time violations have a destination clock path which has a cascaded BUFG from the PLL, and a source clock path which only passes one BUFG after the PLL.
Can this hold time be fixed by Vivado?
This issue is fixed in Vivado 2015.3.
In the meantime, you can rearrange the clock structure to reduce the clock skew as a work-around to resolve the issue.