We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63735

2013.x/2014.x - UNIMACRO - The VHDL MACC_MACRO behaves incorrectly when LATENCY generic is set to 4


When the VHDL MACC_MACRO is instantiated in the design and its LATENCY generic is set to 4, DRC errors like the following are encountered in bitstream generation.

ERROR:[DRC 23-20] Rule violation (REQP-21) enum_AREG_2_connects_CEA1_GND_connects_CEA2_GND_connects_CEA1_connects_CEA2
U0_dpd_acl_top/ACL_0/U1/mult_i/bl.DSP48E_2: When the DSP48E1 AREG attribute is set to 2, the CEA1 and CEA2 input pins cannot be unconnected or tied to GND.

You can also observe unexpected output in simulation.


This is due to incorrect description of CEA1 and CEB1 inputs in the "<Vivado installation directory>\data\vhdl\src\unimacro\MACC_MACRO.vhd" file.

In addition to this one, affected macros include ADDMACC_MACRO.vhd, ADDSUB_MACRO.vhd, EQ_COMPARE_MACRO.vhd.

The equivalent Verilog UNIMACRO library cells do not have this issue.

To work around the DRC issue, manually modify the following two lines in this file.

CEA1_IN <= CE when (AREG_IN = 1) else '0';
CEB1_IN <= CE when (BREG_IN = 1) else '0';

These two lines should be changed to:

CEA1_IN <= CE when (AREG_IN = 2) else '0';
CEB1_IN <= CE when (BREG_IN = 2) else '0';

To obtain correct simulation results, we recommended that as an alternative, you instantiate the DSP48E primitive in the design.

This problem also exists in the ISE UNIMACRO library components for V5, V6 and 7 series devices.

The ISE UNIMACRO library files are located in <ISE installation directory>\ISE\vhdl\src\unimacro.

The work-around for ISE is the same.

This issue is fixed starting in Vivado 2015.3.

AR# 63735
Date 06/10/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Zynq-7000
  • Virtex-5
  • Virtex-6
  • Less
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • More
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4
  • ISE Design Suite
  • Less
Page Bookmarked