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AR# 63740

Vivado Timing Closure – Suggestions for resolving timing issues seen in Vivado


This General Answer Record provides suggestions on how to resolve timing violations seen in Vivado.


Timing Violations due to High Fan-out:

  • Floorplan or LOC the origin and the global buffer of the high fan-out signal.
  • Duplicate the driver and tell the synthesis tool not to remove the duplicate logic.
  • For the signals other than control signals such as reset, set, and clock enable, use max_fanout in Synthesis.
  • Use phys_opt_design that can perform optimization on fan-out. Refer to (Xilinx Answer 53986) for more information.

Timing Violations due to State-machine Optimization:

  • Use one-hot encoding for the states. This is a good choice for optimizing speed.
  • Use a synthesis state machine coding tool, if possible.
  • Reduce the number of input signals and pre-decode the input signals.
  • Register input and output signals.
  • Pre-decode and register counter values.
  • Remove data flow from the state machine and create control signals to control data flow.
  • Duplicate state to where many states transition, and reduce the number of states in state equations.
  • Use CASE statements and not IF-ELSE statements.

Suggestions for long carry logic chains:

  • You can use smaller counters to drive other counters, and cascade them so that the first counter is the enable for the second counter.

Suggestions for levels of logic:

This applies in cases where logic exceeds some percentage of the total path delay, implying that there is too much logic between timing end points; the amount of logic must be reduced in order to meet timing requirements.

To reduce the levels of logic, return to the source and try the following:

  1. Issue State Machine Optimization Suggestions.
  2. Use CASE statements instead of nested IF-ELSE statements.
  3. Use 3-state instead of large muxes (7 or more inputs).
  4. Use creative math; shift instead of multiplying by multiples of two.
  5. Use decoders instead of comparators.
  6. Balance logic around registers.
  7. Pyramid logic with parentheses instead of serial implementation.
  8. Add pipeline registers.
  9. Use IF-THEN-ELSE statements only to do the following:
  • Pre-decode and register counter values.
  • Add a level of pipelining to pre-decode and register input signals
AR# 63740
Date Created 03/01/2015
Last Updated 05/23/2016
Status Active
Type General Article
  • Vivado Design Suite