We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63776

2014.4 - SCUGIC - SCUGIC no longer accepts interrupts on the IRQ port if the PL has been reset


I have a simple design with interrupts connected to the SCUGIC via the IRQ ports on the PS7_PROCESSING_SYSTEM.

However, if I reset the PL (without resetting the PS), then interrupts are no longer detected.

How can I work around this?


If the PL is reset without the PS, then the EOI register on the SCUGIC will need to be cleared in the initialization process of your application.

For example, the line below can be added to the interrupt init in your application:

XScuGic_CPUWriteReg(&InterruptController, XSCUGIC_EOI_OFFSET, XX);

(Where XX is the interrupt ID).

AR# 63776
Date Created 03/03/2015
Last Updated 03/16/2015
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2015.1
  • Processing System 7