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AR# 63784

ERROR: [Shape Builder 18-138] during place_design in Vivado 2014.4


I see the below error when running Implementation, even though I did not specify these LUTNM constraints in my XDC:

ERROR: [Shape Builder 18-138] Cannot obey LUTNM/HLUTNM constraint for instances uearth/unature/u07vrgpu/nx_vr6_core/Inst_04_nx_vr6_pp_top/Inst_16_nx_vr6_pp_fragmentrestore[1]/p0_data[105]_i_14__1 and uearth/unature/u07vrgpu/nx_vr6_core/Inst_04_nx_vr6_pp_top/Inst_16_nx_vr6_pp_fragmentrestore[1]/p0_data[105]_i_18__1. Reason:  for bel A5LUT Element SLICE_X0Y0.A6LUT is not routable as there are 6 input pins and A6 cannot be used because of A5LUT usage..


In this example, the synthesis tool generated incorrect LUTNM constraints. 

Ideally the implementation tool should have issued a warning message regarding incorrect constraints, and proceeded with Implementation, as the resulting design would still be functional.

This issue has been fixed in Vivado 2015.1 so that the placer issues a warning message instead of an error and proceeds with Implementation.

As a work-around in Vivado 2014.4, apply different HLUTNM property values for the problematic LUT instances as below.

set_property HLUTNM group_name1 [get_cells u07vrgpu/nx_vr6_core/Inst_04_nx_vr6_pp_top/Inst_16_nx_vr6_pp_fragmentrestore[1]/p0_data[105]_i_14__1]

set_property HLUTNM group_name2 [get_cells u07vrgpu/nx_vr6_core/Inst_04_nx_vr6_pp_top/Inst_16_nx_vr6_pp_fragmentrestore[1]/p0_data[105]_i_18__1]

AR# 63784
Date Created 03/03/2015
Last Updated 01/04/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2014.4