Version Found:DDR4 v7.0
Version Resolved: See (Xilinx Answer 69035)
When simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model, the following error can occur:
This violation is seen because of an issue with the Micron memory model using the wrong speed bin parameters.
Please use the updated Micron Memory model to avoid these issues.
04/01/2015 - Initial Release