Version Found: DDR3 v7.0
Version Resolved: See (Xilinx Answer 69036)
When simulating a MIG UltraScale DDR3 design using a Micron memory model targeting the sg125 speed grade with CAS Latency = 9 and CAS Write latency = 7, the following error message might be received:
According to the Micron data sheet for the sg125 speed grade, CAS Latency=9 and CAS Write Latency=7 is supported.
Please use the updated Micron Model.
04/01/2015 - Initial Release