Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)
When simulating a MIG UltraScale DDR3 design, the following error message might be seen:
These errors are a result of a known limitation on the MMCM/PLL that results in an alternating period of 1ps variance (i.e. 6000ps, 5999ps, 6000ps, and 6001ps).
This issue occurs for a small subset of input and output clock frequency combinations and can be safely ignored.
04/01/2015 - Initial Release