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AR# 63804

2015.1 XADC Wizard - Example design simulation fails when using DCLK frequency less than 12MHz.


DCLK is supported between the range of 8 - 250MHz.

If running between 8-11MHz the example design simulation fails due to a timing issue with the design.txt file that is created for the example design.


To work around the issue, simulate with a DCLK frequency of 12MHz or greater.

AR# 63804
Date Created 03/05/2015
Last Updated 04/30/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000