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AR# 63813

MIG UltraScale - Is it valid for BISC_ALIGN_NQTR or BISC_ALIGN_PQTR to be '0' across all nibbles?

Description

The UltraScale memory PHYs include BISC which is run at the start of calibration and throughout normal operation to detect and account for skew between internal clocks. 

The  BISC_ALIGN_PQTR / BISC_ALIGN_NQTR and BISC_PQTR_NIBBLE / BISC_NQTR_NIBBLE values are reported through XSDB and can be used to determine the tap resolution for a given nibble. 

Refer to (Xilinx Answer 60305) for information on the usage of these signals.

Is it valid for the results on all BISC_ALIGN_PQTR or BISC_ALIGN_NQTR to be 0 across all nibbles?

Solution

Internal to the PHY there are separate clock paths for rising DQS (PDQS) and falling DQS (NDQS).

Essentially, BISC detects skew between the clocks and balances it by adding taps to the P/NQTR delay on the clock that arrives to endflops first.

The ALIGN value is the added delay.

The XiPHY includes BISC_ALIGN_NQTR and BISC_ALIGN_PQTR.

One will be 0 or some positive value while the other is always 0.


AR# 63813
Date Created 03/05/2015
Last Updated 03/06/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale