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AR# 63844

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v14.3 or earlier - UltraScale SGMII over LVDS - The core does not recover from sporadic application of resets

Description

When using Ethernet 1000BASE-X PCS/PMA or SGMII to target an UltraScale device with SGMII over LVDS, the core does not recover from sporadic application of resets.

Solution

To fix this issue, you will need to connect the following:

  1. Connect Synchronized Reset to the RST pins of idelay elements in the serdes_1_to_10_ser8 module.
  2. Connect the RDY (idelay_rdy) of IDELAYCTRL (present in sgmii_phy_clk_gen) to the idelay_rdy of the module serdes_1_to_10_ser8.
 
Here are the details:
 
1) Changes in <CompName >_serdes_1_to_10_ser8.v file:
 
a.       Add a reset synchronizer on reset, synchronized to rxclk_div4 clock:
 

  <=: CompName :>_reset_sync reset_rxclk_div4 (
     .clk       (rxclk_div4),
     .reset_in  (reset),
     .reset_out (reset_sync)
  );

b.      Connect reset_sync to the RST pin of the following module instances:
 
  • idelay_m
  • idelay_s
  • idelay_cal
c.       Remove the connection of EN_VTC to ~idelay_rdy and tie it instead to 1b0 for the following module instances

  • idelay_m
  • idelay_s
  • idelay_cal
 
2) Changes in <=:CompName :>_sgmii_phy_clk_gen file:
 
VHDL
 
a) Add the idelayctrl_rdy signal as an output port:
 

idelayctrl_rdy : out std_logic;

b) Define the idelayctrl_rdy_i signal:
 

signal idelayctrl_rdy_i : std_logic;

c) Modify the logic of o_mmcm_locked from
 

o_mmcm_locked   <= o_mmcm_locked_i  and idelayctrl_rdy ;

to
 

o_mmcm_locked   <= o_mmcm_locked_i  and idelayctrl_rdy_i ;


d) Change the connection of the rdy pin of the module instance core_idelayctrl_i to idelayctrl_rdy_i.

e) Assign the following:
 

idelayctrl_rdy <= idelayctrl_rdy_i;


Verilog:
 
a) Define the output port idelayctrl_rdy:
 

output wire idelayctrl_rdy,

b) Remove the wire declaration for idelayctrl_rdy.
 

3) Propagate idelay_rdy from the module instance serdes_1_to_10_ser8_i all the way to the level where the module <=:CompName :>_sgmii_phy_clk_gen is instantiated.

Connect delay_rdy to the idelayctrl_rdy port of the instance of the module <=:CompName :>_sgmii_phy_clk_gen
 
4) Changes in gig_ethernet_pcs_pma_0.xdc:
 
Add the following constraint:
 

set_false_path -to [get_pins -hier -filter { name =~ */*reset_rxclk_div*/*sync*/PRE } ] 

AR# 63844
Date Created 03/10/2015
Last Updated 04/08/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • More
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Less
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII