The JESD204 Product Guide (PG066), v6.1, lists the Optional Transceiver Debug Ports for 7 Series (Table 2-14) and UltraScale (2-15) devices.
The clock domain is also listed in these tables.
Two signals (gt_rxlpmen and gt_txdiffctrl) do not have the correct clock domain listed.
The following signals in Table 2-14 and 2-15 are listed as being synchronous to the core clock (either rx_core_clk or tx_core_clk):
These signals are asynchronous inputs to the core and are not synchronous to the core clocks as indicated in (PG066) v6.1.
Table 2-14 and 2-15 should read as follows:
This has been corrected in (PG066) v7.0.