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AR# 63859

MIG - 7 Series - LPDDR2 - Simulation errors seen when simulating a MIG design


Version Found: MIG 7 Series v2.1
Version Resolved: See (Xilinx Answer 54025)

I am receiving the following errors when simulating a MIG design with the default settings:

sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 435261000: Nop or Deselect must be driven in the clock cycle after CKE goes l
sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 867261000: Nop or Deselect must be driven in the clock cycle after CKE goes low

sim_tb_top.mem_rnk[0].gen_mem[0].u_comp_lpddr2.ERROR at time 3503921000: tINIT3 violation


These errors can be safely ignored and will be fixed in MIG v2.3 Rev1.

Revision History:
03/11/2015 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 63859
Date Created 03/11/2015
Last Updated 03/12/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4