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AR# 63862

2014.2 Vivado - Constraint warnings are issued for IP cores that are not included in the top level design


During Synthesis I receive a warning concerning an IP which is not used in the current design.

For Example: 

I am receiving the following message even though ten_gig_eth_pcs_pma_0 is not used under the current top level hierarchy block:

[Vivado 12-180] No cells matched 'get_cells -hier -filter {REF_NAME==ten_gig_eth_pcs_pma_0 || ORIG_REF_NAME==ten_gig_eth_pcs_pma_0}'. ["/projects/project_1/project_1.runs/synth_1/dont_buffer.xdc":4]but ten_gig_eth_pcs_pma_0 is not used in the project.


Vivado should filter out constraint files for IP core that are not being used in the current design hierarchy.

This issue has been fixed in Vivado 2014.3.
AR# 63862
Date 01/12/2017
Status Archive
Type General Article
  • Vivado Design Suite - 2014.2
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