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AR# 63869

7 Series FPGA GTX/GTH/GTP Transceivers - Recommendation on CDR usage for SATA protocol

Description

While SATA link is initializing, a Transceiver will be in electrical idle state.

However, RX CDR will continue to look for data transition on RXP/RXN lines which may result in
large phase offset on the recovered clock (RXOUTCLKPMA).

This could eventually result in a wrong frequency or flat line of RXOUTCLK which will cause SATA linkup failure.

This answer record provides guidance to avoid this failure condition.

Solution

During SATA link initialization, it is recommended to keep CDR in hold state by setting RXCDRDHOLD=1'b1.

This will ensure RXOUTCLK is stable during and after the reset sequence.

RXCDRHOLD should be deasserted after RXELECIDLE is LOW (Please refer to the "RX Out-of-Band Signaling" section in (UG476)/(UG482) for the algorithm to determine whether the RX is in electrical idle).

It is recommended to monitor the RXELECIDLE=LOW condition for at least 20 USRCLK cycles before setting RXCDRHOLD to 1'b0.

This recommendation is specific to the SATA use case.

The PCIexpress protocol (which also keeps transceivers in electrical idle state during initialization) is not impacted by this issue because CDR is not set to track SSC. 

The Transceiver user guides (UG476)/(UG482) will be updated with this recommendation in the next release.

Revision History:
04/16/2015 - Initial Release

AR# 63869
Date Created 05/29/2015
Last Updated 05/11/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex UltraScale
  • More
  • Kintex UltraScale
  • Virtex-7
  • Less
Tools
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2015.1
IP
  • 7 Series FPGAs Transceivers Wizard