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AR# 63874

2014.4 Partial Reconfiguration - place_design fails in 2nd configuration, but the initial configuration with same RM DCPs completes without error

Description

In the initial and second configuration of my design, the same Reconfigurable Module (RM) DCP files are used.
 
The initial configuration completes without error, but place_design fails with the following error in the second configuration:
 
ERROR: [Place 30-487] The packing of instances into a set of slices defined by a pblock constraint could not be obeyed. Please analyze your design to determine if the pblock can be resized or the number of LUTs, FFs, and/or control sets can be reduced.
Pblock name: "pblock_u0_umdu_pr_top"
Pblock range: RAMB36_X10Y35:RAMB36_X10Y49
RAMB36_X3Y30:RAMB36_X9Y49
RAMB18_X10Y70:RAMB18_X10Y99
RAMB18_X3Y60:RAMB18_X9Y99
PCIE_X0Y0:PCIE_X0Y0
DSP48_X4Y60:DSP48_X10Y99
SLICE_X168Y150:SLICE_X171Y249
SLICE_X162Y175:SLICE_X167Y249
SLICE_X64Y150:SLICE_X161Y249
Number of instances constrained to the pblock:
 Flip flops: 11911 in the design area under consideration, 83600 available in the area constraint (NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice)
 Luts: 4902(combined) 4902 (total) in design area under consideration, 41800 available in area constraint
 Control sets: 234 in area constraint
The unplaced instances require 3288 slices but only 3267 out of 10450 slices in the pblock are available, because others may be occupied by placed instances or blocked due to exclude placement constraints.
 Names of cells:
  u0_umdu_pr_top
To attempt placement at higher effort levels at the expense of runtime, please use the following tcl command, setting the value of limit to 2000 or more.
set_param place.sliceLegEffortLimit limit
 PS: Please note that the legalization failed due to an internal merged constraint, so the utilization and occupancy above is for the merged constraint which covers the following clock regions only.
   CLOCKREGION_X0Y3
   CLOCKREGION_X1Y3
   CLOCKREGION_X0Y4
   CLOCKREGION_X1Y4

Solution

The issue will be fixed in Vivado 2015.2.
AR# 63874
Date Created 03/12/2015
Last Updated 04/16/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4