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AR# 63876

7 Series FPGA and Zynq-7000 AP SoC HR I/O Transition at the End of Startup


In 7 Series devices with multi-function HR I/O in banks 14 and bank 15, if the following conditions are met then the input might have an internal 0-1-0 transition to the interconnect logic during configuration startup:

  • the VCCO for the multi-function bank is 1.8V or lower
  • A pin in that bank, that has both a configuration function as well as a User I/O function, is Low or floating

Because this transition occurs after GWE enables the internal logic, it might affect the internal state of the device after configuration.

In a 7 series FPGA, this transition can occur at EOS (End Of Startup).

The HR I/O bank 34 and bank 35 in the Zynq-7000 AP SoC PL can have similar behavior.

No action is required for logic that is not impacted by input transitions during startup, (for example, logic that does not register inputs during startup or that is reset through/after startup).

Affected Implementations:

The affected 7 Series FPGAs and Zynq-7000 AP SoCs and HR I/O banks are shown in Table 1:

Table 1 - 7 Series FPGAs and Zynq-7000 AP SoCs and HR I/O Banks Affected by Transition during Configuration Startup

A 7 series FPGA or Zynq-7000 AP SoC design can be affected when ALL of the following are TRUE:

  • Device = Artix-7 FPGA or Kintex-7 FPA or Zynq-7000 AP SoC
  • VCCO_0 = 3.3V or 2.5V (i.e. when CFGBVS=VCCO_0)
  • Artix-7 or Kintex-7 VCCO_14 = 1.8V or lower, or Artix-7 or Kintex-7 VCCO_15 = 1.8V or lower, or Zynq-7000 VCCO_34 = 1.8V or lower, or Zynq-7000 VCCO_35 = 1.8V or lower
  • The input pin state is Low or floating during configuration startup
  • User design is impacted by a 0-1-0 input transition during configuration startup
  • The I/O is a multi-function I/O that has a configuration function in addition to a user I/O function


When ALL of the above are TRUE, the internal signal from an input pin in an affected bank, might have a 0-1-0 transition at end of startup (EOS).

This internal input signal transition can affect the state of internal logic.

The internal input signal is clear of the potential transition by 200 nS after EOS.

                                          Figure 1 HR I/O Bank 14/15/34/35 Potential Input Transition Window at EOS


Multiple options for work-arounds are available, including the following:

  • Use the same voltage across VCCO_0 and VCCO_14/_15/_34/_35 in the PCB design.
  • Keep affected bank 14/15/34/35 input pins at a High state from startup through at least the end of the affected window of time near EOS.
  • Include logic in a synchronous FPGA design that delays the start of the clock(s) to the affected logic until at least the end of the affected window of time following EOS.
  • Include logic in the FPGA design that ignores affected input signals from startup through at least the end of the affected window of time following EOS.

For the FPGA design work-arounds, an IGNORE_INP_B signal can be created using an EOS signal from the STARTUPE2 primitive and a suitably long counter or shift register to either delay the clock(s) to the affected logic or gate the affected input signals.

The active-High EOS output signal from the STARTUPE2 primitive signifies the end of configuration startup which begins the affected window of time.

Example block diagrams of potential FPGA design work-arounds are shown in Figure 2 and Figure 3, below.

Note: Figure 3 is a simplified, conceptual example.

Input gating can be implemented differently to assure release synchronous to logic clock(s).

AR# 63876
Date 07/13/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
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