Version Found: MIG 7 Series v2.0 Rev 3
Version Resolved: See (Xilinx Answer 54025)
To work around it, increase or decrease the system clock period by 1ps.
If the warnings are noticed in simulation, change the system clock time period to +/-1 PS in the top level RTL file.
For implementation, both the XDC and top level RTL files should be modified.