UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63914

AXI Ethernet v6.2 or earlier - UltraScale - SGMII over LVDS - Synchronization and reset issue

Description

When using AXI Ethernet on an UltraScale device with SGMII over LVDS, synchronous SGMII is not stable.

There are synchronization and reset issues.

 

Please note: this Answer Record is for AXI Ethernet IP from the IP Catalog. 

The flow for an IPI design is different.  


An AXI Ethernet SGMII over LVDS design with the option "Shared Logic in Example Design" requires an idelay control element which is not currently present in the IPI catalog. 

You will need to add this idelay control element as a local pcore before connection.

Please see (Xilinx Answer 64142) for more details.

Solution

To work around this issue, follow the steps below:
 
Generate the AXI Ethernet from the IP Catalog.

After generating the output products of AXI Ethernet, generate the AXI Ethernet example design and edit the below files:
 
Use the following command in the Vivado Tcl prompt:
get_files *serdes_1_to_10_ser8.v

or
 
Go to the sub-core directory: *axi_ethernet.srcs/sources_1/ip/axi_ethernet_0/bd_1/ip/ip_2/synth/sgmii_lvds_transceiver and edit bd_1_pcs_pma_0_serdes_1_to_10_ser8.v
 
Make the changes outlined in (Xilinx Answer 62072)
 
Connect 1b0 to enable_monitor of delay_controller_wrap in _serdes_1_to_10_ser8.v              
 
Make the changes outlined in (Xilinx Answer 63844)
 
1)

Changes in <CompName >_serdes_1_to_10_ser8.v file
 
Add a reset synchronizer on reset, synchronized to rxclk_div4 clock
 

               <=: CompName :>_reset_sync reset_rxclk_div4 (
         .clk       (rxclk_div4),
         .reset_in  (reset),
         .reset_out (reset_sync)
               );

b.  Connect reset_sync to the RST pin of the following module instances:
 
  • idelay_m
  • delay_s
  • idelay_cal
c.  Remove the connection from EN_VTC to ~idelay_rdy and tie it instead to 1b0 for the following module instances:

  • idelay_m
  • idelay_s
  • idelay_cal
 
2)

Go to example design directory:
 
axi_ethernet_0_example/axi_ethernet_0_example.srcs/sources_1/imports/example_design

Changes in <=:CompName :>_ support_clocking.v file:
 
  • Define output port idelay_ctrl_rdy
    output idelay_ctrl_rdy,
  • Remove wire declaration for idelay_ctrl_rdy
 
3)

Propagate idelay_rdy from the module instance serdes_1_to_10_ser8_i all the way to the level where the module <=:CompName :>_ support_clocking is instantiated.

Connect delay_rdy to the idelay_ctrl_rdy port of instance of module <=:CompName :>_support_clocking
 
AR# 63914
Date Created 03/13/2015
Last Updated 04/03/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
IP
  • AXI Ethernet