I am trying to look at the hierarchy of an IP core I created in the Vivado Hierarchical Source View (HSV).
However, I am not able to expand the hierarchy of an XCI file that is created as a sub-block of another IP core.
If I generate an example design with PCIe Gen3 on UltraScale Virtex, I see the Show Hierarchy button is grayed out and the Hierarchy of the *gt.xci does not display.
the *gt.xci is a lower level file, which is under the pcie3_ultrascale_0.xci.
Vivado will have a problem displaying the hierarchy of a sub-core IP module if the upper level IP core hierarchy is expanded by itself first.
To work around this issue, do the following: