We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63945

Vivado UltraScale Partial Reconfiguration - How to create the pblock of Reconfigurable Partitions straddling SLRs


What should I pay attention to when I intend to create a pblock for Reconfigurable Partitions crossing Super Logic Regions (SLR)?


A Reconfigurable Partition's pblock that spans SLRs must be wide and high enough to grab the whole column of Laguna sites.

Failure to grab enough Lagunas can make the design unroutable.

The following DRC HDPR-54 will be triggered if the pblock fail to obey this rule:

HD.RECONFIGURABLE Pblock 'pblock_U1' is not entirely contained within a single Super Logic Region (SLR) and does not contain any LAGUNA resources to cross from one SLR to the other.

An entire column of LAGUNAs within a clock region on either side of the SLR is required for this pblock. Please include a LAGUNA range for this pblock or keep the pblock within a single SLR.

In the following example design, all of the LAGUNA columns are not selected completely, which is illegal:


Note: The highlighted area is the LAGUNA site.

AR# 63945
Date 07/18/2017
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite
Page Bookmarked