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AR# 63956

2015.x Vivado Simulator - Known Issues

Description

This answer record lists the known issues for the Vivado Simulator in the Vivado 2015.x releases.

Each known issue includes a link to another answer record that contains additional information on the issue.

Solution

Outstanding Issues in Vivado 2015.4

(Xilinx Answer 66061) Vivado 2015.3/2015.4 - export_simulation ignoring -lib_map_path option in Windows
(Xilinx Answer 66062) Vivado Simulator 2015.4 - FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover
(Xilinx Answer 65571) Vivado 2015.3/2015.4 - Export Simulation script with single step option fails for Cadence IUS


Issue resolved in Vivado 2015.4

(Xilinx Answer 65716) 2015.3 - ModelSim cannot find the include directory when launching simulation from Vivado GUI in Windows platform


Outstanding Issues in Vivado 2015.3

(Xilinx Answer 65572) 2015.3 - Vivado - Exported simulation script fails for design with HLS and Sysgen IP
(Xilinx Answer 65564) 2015.3 Vivado - Mem file not copied to simulation directory - ERROR: [VRFC 10-451] cannot open file 'int_infile
(Xilinx Answer 65453) Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation
(Xilinx Answer 65716) 2015.3 - ModelSim cannot find the include directory when launching simulation from Vivado GUI in Windows platform
(Xilinx Answer 66061) Vivado 2015.3/2015.4 - export_simulation ignoring -lib_map_path option in Windows
(Xilinx Answer 64138) 2015.2: Vivado simulator not honoring concurrent assert statement when there is time expression (NOW)
(Xilinx Answer 65571) Vivado 2015.3/2015.4 - Export Simulation script with single step option fails for Cadence IUS

Outstanding Issues in Vivado 2015.2

(Xilinx Answer 64738) 2015.1/2015.2 Vivado Simulator - crash occurs if arrow key is pressedafter deleting a signal in waveform window
(Xilinx Answer 65250) 2015.x Vivado Simulator - Crash occurs at the beginning of simulation on Windows platform for large design
(Xilinx Answer 65453) Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation
(Xilinx Answer 64138) 2015.2: Vivado simulator not honoring concurrent assert statement when there is time expression (NOW)

Issues resolved in Vivado 2015.2

(Xilinx Answer 64665) 2015.1 Vivado Simulator - Webtalk appears to be getting ran even though it is disabled

Outstanding Issues in Vivado 2015.1

(Xilinx Answer 63958) 2015.1 Vivado Simulator - print format specifier %p does not work on associative array
(Xilinx Answer 63959) 2015.1 Vivado Simulator - No error is issued for illegal array assignment
(Xilinx Answer 63971) 2015.1 Vivado Simulator - ERROR: [VRFC 10-1466] type time does not match with the integer literal
(Xilinx Answer 63792) 2015.1 Vivado Simulator - Elaboration fails when GTHE3_CHANNEL/GTHE3_COMMON's SIM_VERSION parameter is set to 2
(Xilinx Answer 63973) 2015.1 Vivado Simulator - VHDL natural port connected to Verilog net is unsupported
(Xilinx Answer 63984) 2015.1 Vivado Simulator - Simulation using DPI fails in Ubuntu OS
(Xilinx Answer 63224) Vivado simulator - Error "[VRFC 10-454] cannot open vhdl file" may occur in Windows OS when running behavioral simulation on IP Example Design
(Xilinx Answer 63735) 2013.x/2014.x - UNIMACRO - The VHDL MACC_MACRO behaves incorrectly when LATENCY generic is set to 4
(Xilinx Answer 63628) Does Vivado Simulator support tracing of VHDL variables?
(Xilinx Answer 63337) VCS - Error-[EIRO] Illegal real operand rxtx_bitslice_002.vp, 1
(Xilinx Answer 64333) Vivado - Breakpoint setting does not work in GUI when the source file has space in its path
(Xilinx Answer 64349) Vivado Simulator does not compile a module even though it is included in project and is marked for use in simulation
(Xilinx Answer 65250) 2015.x Vivado Simulator - Crash occurs at the beginning of simulation on Windows platform for large design
(Xilinx Answer 65453) Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation


Issues resolved in Vivado 2015.1

(Xilinx Answer 62583) 2014.x Vivado Simulator - xelab rangecheck might cause some IP cores to fail to elaborate by being too strict in handling VHDL null vectors
(Xilinx Answer 62969) 2014.4 Vivado Simulator - ERROR: [USF-XSim-62] 'elaborate' step failed with error(s) in Windows platform due to large concatenation of signals
(Xilinx Answer 62898) Vivado Simulator 2014.4 Linux : Waveform viewer crashes when selecting all signals and then deleting them
(Xilinx Answer 62857) 2014.3 Vivado Simulator - WCFG file added to my Vivado project as a simulation source does not open when simulation is ran
(Xilinx Answer 62469) 2013.x/2014.x UNIMACRO - ADDSUB_MACRO behaves incorrectly in simulation when LATENCY is < 2
(Xilinx Answer 63044) 2014.3/4 Vivado Sysgen - Tactical Patch for Sysgen crashing due to webtalk issue when Vivado Simulator is called
(Xilinx Answer 64350) Vivado 2014.x - compile_simlib fails when compiling to a directory with space
(Xilinx Answer 64353) 2014.x Vivado Simulator - SAIF dumping for a top level that has no ports fails by enabling xsim.simulate.saif in Simulation Settings

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58798 Xilinx Simulation Solution Center - Top Issues N/A N/A
63538 Vivado Design Suite 2015 - Known Issues N/A N/A

Child Answer Records

AR# 63956
Date Created 03/19/2015
Last Updated 04/18/2016
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.4