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AR# 63972

2015.1 Vivado Simulator - Elaboration fails when GTHE3_CHANNEL/GTHE3_COMMON's SIM_VERSION parameter is set to 2

Description

For UltraScale designs, when the parameter SIM_VERSION of GTHE3_CHANNEL and GTHE3_COMMON is set to 2, the elaborate step fails with the following error:

[XSIM 43-3241] File /proj/buildscratch/builds/2014.4/continuous/20141118161353/data/secureip/gthe3_channel/gthe3_channel_002.vp, Line Num 42508, Node sysclk01C4zero is not annotated.

Solution

This is a known issue with the Verilog Compiler of Vivado Simulator. 

Overriding the parameter with the values 1, 3, or "Ver_1" allows elaboration to complete without error.

This is scheduled to be fixed in a future release.
AR# 63972
Date Created 03/20/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1