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AR# 63973

2015.1 Vivado Simulator - VHDL natural port connected to Verilog net is unsupported

Description

In a mixed-language design, if a lower level VHDL natural port is connected to a Verilog net in the top level, I receive an error message similar to the following:

[VRFC 10-717] formal port dout of type natural does not match with actual type wire

Solution

Currently this use case is not supported by Vivado Simulator.

It is scheduled to be fixed in a future release.
AR# 63973
Date Created 03/20/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1