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AR# 63975

AHB-Lite to AXI4 Bridge - HREADY signal is ignored during bursts


During a 16 long AHB burst the Slave (the bridge in this case) can insert wait states at any time. 

The Bridge usually inserts some wait states during operation, but the interface ignores it and continues sampling data and incrementing the burst counter.

As a result the bridge will think that the burst is finished earlier than it is actually and has wrong data in some places. 

Then it will block the remaining part of the burst for a long time by holding HREADY down.


The connection chain where the issue came up is:
AHB interconnect Master port -> Xilinx AHBLite2AXI Bridge IP -> Xilinx PCIe IP Slave port


To fix the issue, feedback 's_ahb_hready_out' to 's_ahb_hready_in' in the design.

Please see the following link from the ARM website where it is suggested that 's_ahb_ready_out' needs to be fedback to 's_ahb_hready_in'.


Typically an AHB slave would be connected to an AHB master through an AHB mux.

In this situation, the AHB mux will provide HREADY_IN to slave and this signal will tell whether the previous selected slave has finished the transfer or not.

The AHB slave on its own, cannot know whether it is connected to an AHB mux or directly to an AHB master, so it would always expect the user to provide this input. 

Tying 0 or 1 will make the IP function incorrectly. 

When you do not have an AHB mux in between the Master & Slave, you should feed back HREADYOUT as HREADY_IN.

AR# 63975
Date 06/09/2015
Status Active
Type General Article
  • Zynq-7000
  • Artix-7
  • Kintex UltraScale
  • More
  • Kintex-7
  • Virtex UltraScale
  • Virtex-7
  • Less
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • AHB-Lite to AXI Bridge
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