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AR# 63985

How to run behavioral simulation using Vivado Simulator?


Behavioral simulation at the Register Transfer Level (RTL) lets you simulate and verify your design prior to any translation made by synthesis or implementation tools.

It is typically performed to verify code syntax, and to confirm that the code is functioning as intended. 

This article describes the two ways to run behavioral simulation using Vivado Simulator: from the Vivado IDE and from the command line.


Vivado IDE:
  1. Create a Vivado RTL project.
  2. Create and add simulation sources.
  3. Specify Vivado Simulator Simulation Settings if necessary.
  4. From the Flow Navigator, select Run Simulation > Run Behavioral Simulation

Command Line:
  1. Parse design files using the xvhdl/xvlog command.
  2. Elaborate and generate a design snapshot using the xelab command.
  3. Simulate the design snapshot using the xsim command.

For Example:
xvlog file1.v
xvhdl file2.vhd
xvlog top.v
xelab -debug typical top -s top_sim
xsim top_sim -gui -t xsim_run.tcl
Alternatively, you can put the HDL sources in a project file (.prj), and parse the project file.
For Example:

xelab -prj tb_beh.prj -debug typical top -s top_sim
xsim top_sim -gui -t xsim_run.tcl

Use the following syntax inside the project file:
verilog <work_library> <file_names>... [-d <macro>]...[-i <include_path>]...
vhdl <work_library> <file_name>
sv <work_library> <file_name>
RTL simulation is not architecture-specific unless the design contains an instantiated device library component.
If it does, you will need to specify the -L switch in the xelab command for each search library.
Also, the glbl module will need to be compiled and loaded along with the design top.
For example:

xvlog $XILINX_VIVADO/data/verilog/src/glbl.v

xelab -debug typical -L secureip -L unisims_ver -L unimacro_ver top glbl -s top_sim 

If a design has been compiled to be completely non-debuggable for faster performance (either by not specifying -debug <options> or by specifying "-debug off" to the xelab command line), then if you run xsim -gui <snapshot> and try tracing the waveform, the waveform window stays blank. 

For more information on using Vivado Simulator and the command line options, please refer to (UG900) Vivado Design Suite User Guide: Logic Simulation.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 63985
Date Created 03/22/2015
Last Updated 05/05/2015
Status Active
Type General Article
  • Vivado Design Suite