UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63997

2014.4 UltraScale Hierarchical Design - False DRC (RTSTAT-2) is reported that out_of_context clock is unrouted or partially routed

Description

In an out_of_context (OOC) design targeting on UltraScale device, the following DRC is reported for the clock signal:

ERROR: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are XX_clk.

Is this DRC correct?

Solution

DRC should not report OOC clocks as unrouted or partially routed in UltraScale. 

In Vivado 2015.1, this DRC will be removed for these circumstances.

You can work around this issue in Vivado versions prior to 2015.1 by reducing the severity of the RTSTAT-2 check: 

set_property severity warning [get_drc_checks RTSTAT-2] 
AR# 63997
Date Created 03/23/2015
Last Updated 04/02/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4