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AR# 63998: 2015.1 Vivado UltraScale Partial Reconfiguration - Can the BUFG in the static region drives BUFG loads in the reconfigurable module
2015.1 Vivado UltraScale Partial Reconfiguration - Can the BUFG in the static region drives BUFG loads in the reconfigurable module
In a Partial Reconfiguration design targeting an UltraScale device, can the BUFG in the static region drive BUFG loads (BUFGCE, BUFG_GT or BUFGCTRL) in the reconfigurable module?
This connection is now illegal.
From Vivado 2015.1, DRC HDPR59 is added to avoid this type of topological structure:
Rule violation (HDPR-59) Illegal clock load '<name>' found on PR boundary clock net '<name>'. Static clock nets are not allowed to drive loads inside of a reconfigurable region of type BUFGCE, BUFG_GT or BUFGCTRL. Remove the series buffer inside of the PR region to correct this issue.