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AR# 64019

Vivado Synthesis - ASYNC_REG is not getting applied to the registers when applied on net signals in HDL

Description

ASYNC_REG is not getting applied to the registers when applied on net signals in HDL as shown below.

        type Reg_Array is array ( CONST_PIPE_STAGES - 1 downto 1 ) of std_logic;
signal sl_arr_RegBank_InOuts : Reg_Array := ( others => '0' );
attribute ASYNC_REG : string;
attribute ASYNC_REG of sl_arr_RegBank_InOuts: signal is "TRUE";
        begin

        Register_Pipes:
for I in 0 to CONST_PIPE_STAGES - 1 generate 
FFfirst: 
if I = 0 generate First_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
(       C => IN_CLK,
CE => '1',
R => '0',
D => IN_DATA, 
Q => sl_arr_RegBank_InOuts( 1 )
);
end generate;
FFmid: 
if I > 0 AND I < CONST_PIPE_STAGES - 1 generate Mid_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
( C => IN_CLK,
CE => '1',
R => '0',
D => sl_arr_RegBank_InOuts( I ), 
Q => sl_arr_RegBank_InOuts( I + 1 )
);
end generate;
FFlast: 
if I = CONST_PIPE_STAGES - 1 generate Last_FF : FDRE
generic map (  INIT => '0'  ) 
port map 
( C => IN_CLK,
CE => '1',
R => '0',
D => sl_arr_RegBank_InOuts( CONST_PIPE_STAGES - 1 ), 
Q => OUT_DATA
);
end generate;
end generate;

Solution

This is expected behavior.

The ASYNC_REG property can only be applied on cells.

In the example above it is applied on net signals that are connecting between register instances and so is ignored.

For this particular example, there is no option to apply it on the cells through RTL because the FDRE primitive is instantiated inside a generate loop.

If there is no generate block, then the attribute can be applied on the cells/instances. 

The work-around here is to apply the constraint on cells through XDC. 
AR# 64019
Date Created 03/24/2015
Last Updated 04/08/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite