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AR# 64030

Vivado Synthesis - MAX_FANOUT applied on only one bit of a wide bus in XDC gets annotated to the other bits

Description

If I apply the MAX_FANOUT attribute in XDC for only one bit of a wide bus, the MAX_FANOUT property gets annotated to rest of the bits.

For example, I have a 10-bit wide bus (fanout_bus), and I want to replicate one of the bits (for example, the LSB).

This can be done as follows in the XDC file:

set_property MAX_FANOUT 20 [get_cells {fanout_bus_reg[0]}]


Currently the tool accepts the attribute and replicates the net to meet the fanout described above, but in turn this also replicates the nets of [9:1] if they have higher fanout (>20).

Solution

To work around this issue, change the RTL and create a temporary net, then apply the MAX_FANOUT attribute to it.

You can create temporary signals using the following example which separates 9-bits and the 1-bit which we want to replicate.
 
reg [9:1] fanout_bus_1;
reg fanout_bus_0;

always@(posedge clk)
begin
   fanout_bus_1 <= din[9:1];
   fanout_bus_0 <= din[0];
end

wire [9:0] fanout_bus;
assign fanout_bus = {fanout_bus_1,fanout_bus_0};

Apply the MAX_FANOUT attribute via XDC as follows for the modified net:
 
set_property MAX_FANOUT 20 [get_cells {fanout_bus_0_reg}]
In the RTL, you can use the following:
 

(* max_fanout = 20 *) reg fanout_bus_0;

AR# 64030
Date Created 03/24/2015
Last Updated 04/09/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite