When an OOC module/entity is used, if there are ports on that level that are not bits or vectors, the following error could be received when the Vivado Netlist Tool tries to put the top level and OOC module together:
The error points out a port type mismatch between the OOC module/entity and its instantiation in the parent level.
What is the reason for this error?
How can I resolve it?
This error occurs because when synthesis runs on the OOC module, the top level ports all get converted to Standard Verilog constructs for ports - bits or vectors.
So if there were 2-D arrays or records or structures on those levels, they no longer exist after the OOC module has been synthesized.
Then when the top level instantiates the OOC module, the ports no longer match and therefore the error occurs.
The OOC flow should never be used with OOC module ports other than bits or vectors.
The solution is to either change the OOC flow to not have advanced types of ports, or to write a wrapper file that will hook up the advanced structures with the new ports that have been created.