This is an expected synthesis behavior.
treats 'X' & 'U' as "don't cares".
As a result, the tool interprets them as either '1' or '0' with a primary goal of providing a better QOR.
The generated netlist might also mismatch with the original RTL expectation, causing simulation mismatches.
For these reasons and for good coding style practice, it is recommended to avoid the use of X' or 'U' comparison in the VHDL code with Vivado synthesis.