We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64042

Vivado Synthesis - Recommendations on 'X' and 'U' comparison in VHDL


Vivado Synthesis generates an incorrect logic netlist when synthesizing a VHDL code involving 'X' and 'U' comparison.

Why is this happening?

What is the recommended use with Vivado Synthesis?


This is an expected synthesis behavior. 

Vivado Synthesis treats 'X' & 'U' as "don't cares".

As a result, the tool interprets them as either '1' or '0' with a primary goal of providing a better QOR.

The generated netlist might also mismatch with the original RTL expectation, causing simulation mismatches.

For these reasons and for good coding style practice, it is recommended to avoid the use of X' or 'U' comparison in the VHDL code with Vivado synthesis.

AR# 64042
Date Created 03/25/2015
Last Updated 04/09/2015
Status Active
Type Known Issues
  • Vivado Design Suite