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AR# 64047

2015.1 Vivado UltraScale Speed files - GTH/Y - CRITICAL WARNING: [Timing 38-317] MAX_SKEW violations found between GTHE3_CHANNEL pins TXUSRCLK2 and TXUSRCLK

Description

When I run timing analysis on my post-routed design, I receive the following warning:

CRITICAL WARNING: [Timing 38-317] MAX_SKEW violations found between GTHE3_CHANNEL pins TXUSRCLK2 and TXUSRCLK

How do I remove this critical warning?


Solution

This issue is known to impact some UltraScale GT interfaces.

  • If you are getting this warning in Vivado version 2015.3 or greater, and are targeting a production device, ensure that you are following the recommended GT [RT]XUSRCLK[2] Clocking topologies listed below.
  • If you are getting this warning in Vivado version 2015.3 or greater, and are targeting a ES2 device, see the section on ES2 device MAX_SKEW violations below.

Background:

For GT designs that use individual clock buffers with different divider settings for GT[YH]E3_CHANNEL TXUSRCLK/TXUSRCLK2 pin pairs or RXUSRCLK/RXUSRCLK2 pin pairs, there is a newly updated max skew constraint (see the example below):

 


The following GT clocking configurations can cause MAX_SKEW timing violations for TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pin pairs:

  • Multi-quad interfaces where the GT[YH]E3_CHANNEL that provides the master clock drives GT[YH]E3_CHANNEL more than two clock regions above or below
  • GT interfaces where the TXUSRCLK2 or RXUSRCLK2 loads are spread out over several vertical clock regions
  • GT interfaces where the TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pin pairs are not clocked from BUFG_GT pairs on the same side of the chip as the destination GTs

Note: MMCM generated clocks are not recommended to drive TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pin pairs. The BUFG_GT has built-in dynamic clock division capability that you can use in place of an MMCM for clock rate changes.

Recommended GT [RT]XUSRCLK[2] Clocking Topologies

To ensure that the MAX SKEW constraint passes on [RT]XUSRCLK[2]/[RT]XUSRCLK[2] pin pairs, please check for the following:

1) Ensure that TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pin pairs are clocked from a master channel that is on the same side of the device.

2) Ensure that the master channel BUFG_GT pairs are driving the GT[YH]E3_CHANNEL TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pin pairs within a maximum distance of two horizontal clock regions.

3) Ensure that the BUFG_GT pair that is driving the TXUSRCLK/TXUSRCLK2 pair or the RXUSRCLK/RXUSRCLK2 pair is located in either the top half or the bottom half of the 24 BUFG_GT sites of the Quad.

The examples below show a left side and a right side GT interface with ideal BUFG_GT grouping selected.

The BUFG_GT sites are marked in Cyan and the BUFG_GT pairs driving the TXUSRCLK/TXUSRCLK2 pairs are marked in Red and are assigned to the ideal location for each interface to minimize skew.



4) If TXUSRCLK2 or RXUSRCLK2 loads are spread over too many clock regions vertically, max skew violations might still occur between TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 pairs even after following the previous recommendations.

In that case you can do the following:

a.      Restrict the TXUSRCLK2 or RXUSRCLK2 loads to a tighter vertical spread around the load GTs using pblocks or other user constraints.

b.      Duplicate the TXUSRCLK2 or RXUSRCLK2 BUFG_GT buffers and separate the GT loads from the user logic loads.

One BUFG_GT will drive the GTs and another BUFG_GT will drive the user logic.

This will minimize the clock skew between the TXUSRCLK/TXUSRCLK2 or RXUSRCLK/RXUSRCLK2 BUFG_GT pairs that drive the GTs.

The timing engine and implementation tools correctly handle any skew between the BUFG_GTs driving the GT loads and the BUFG_GTs driving the user logic.

The picture below shows an example of a TXUSRCLK2/TXUSRCLK pair with split BUFG_GT buffers for the TXUSRCLK2 clock.

One BUFG_GT is driving the TXUSRCLK2 clock back to the GT, the other BUFG_GT is driving the TXUSRCLK2 user logic loads.



ES2 device MAX_SKEW violations in Vivado 2015.3 and above:

In Vivado 2015.3 the placer algorithm was updated to meet the MAX_SKEW requirement for production devices, which have an updated GT [RT]XUSRCLK[2] MAX_SKEW requirement.


ES2 devices have to meet the same requirement and use the same placer algorithm.  However, speed files for ES2 devices were not updated with the new MAX_SKEW requirement in Vivado 2015.3 and therefore you might get false MAX_SKEW violations for ES2 devices.


If you are getting a MAX_SKEW violation for ES2 devices in Vivado 2015.3, use the script below to generate a MAX_SKEW report for the Fast and Slow corner of the device and compare the actual skew vs. the new MAX_SKEW requirement from the "New Requirement" column in the table below.

If the actual skew is below the MAX_SKEW requirement in the table below, you can safely ignore the MAX_SKEW violation.

If you followed the recommended GT [RT]XUSRCLK[2] clocking topology, you should not violate the updated MAX_SKEW requirement in the table below.

# run analysis in Slow corner

config_timing_corners -corner Fast -delay_type none

config_timing_corners -corner Slow -delay_type min_max

report_pulse_width -max_skew -file max_skew_Slow_ES2.txt -append -no_head [get_pins -filter REF_PIN_NAME=~RXUSRCLK* -of [get_cells -hier -filter LIB_CELL=~GT*CHANNEL]]

report_pulse_width -max_skew -file max_skew_Slow_ES2.txt -append -no_head [get_pins -filter REF_PIN_NAME=~TXUSRCLK* -of [get_cells -hier -filter LIB_CELL=~GT*CHANNEL]]

# run analysis in Fast corner

config_timing_corners -corner Fast -delay_type min_max

config_timing_corners -corner Slow -delay_type none

report_pulse_width -max_skew -file max_skew_Fast_ES2.txt -append -no_head [get_pins -filter REF_PIN_NAME=~RXUSRCLK* -of [get_cells -hier -filter LIB_CELL=~GT*CHANNEL]]

report_pulse_width -max_skew -file max_skew_Fast_ES2.txt -append -no_head [get_pins -filter REF_PIN_NAME=~TXUSRCLK* -of [get_cells -hier -filter LIB_CELL=~GT*CHANNEL]]

# check max_skew_Slow_ES2.txt and max_skew_Fast_ES2.txt vs. the updated skew requirement

 

2015.3 MAX_SKEW requirements

Speed Grade Check Type Corner Lib Pin Reference Pin New Requirement Old Requirement
-1 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.797 0.497
-1 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.507 0.497
-1 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.899 0.497
-1 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.648 0.497
-1 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.630 0.348
-1 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.411 0.348
-1 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.662 0.348
-1 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.518 0.348
-2 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.672 0.516
-2 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.367 0.516
-2 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.675 0.516
-2 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.517 0.516
-2 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.630 0.348
-2 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.411 0.348
-2 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.662 0.348
-2 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.518 0.348
-3 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.676 0.516
-3 Max Skew Slow GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.401 0.516
-3 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.735 0.516
-3 Max Skew Slow GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.543 0.516
-3 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK2 GTYE3_CHANNEL/RXUSRCLK 0.630 0.348
-3 Max Skew Fast GTYE3_CHANNEL/RXUSRCLK GTYE3_CHANNEL/RXUSRCLK2 0.411 0.348
-3 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK GTYE3_CHANNEL/TXUSRCLK2 0.662 0.348
-3 Max Skew Fast GTYE3_CHANNEL/TXUSRCLK2 GTYE3_CHANNEL/TXUSRCLK 0.518 0.348
 
Speed Grade Check Type Corner Lib Pin Reference Pin New Requirement Old Requirement
-1LV Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.544 0.497
-1LV Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.724 0.497
-1LV Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 1.160 0.497
-1LV Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.733 0.497
-1LV Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.348
-1LV Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.348
-1LV Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.348
-1LV Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.348
-1 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.328 0.497
-1 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.530 0.497
-1 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.864 0.497
-1 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.613 0.497
-1 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.348
-1 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.348
-1 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.348
-1 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.348
-2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.005 0.516
-2 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.516 0.516
-2 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.575 0.516
-2 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.516 0.516
-2 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.348
-2 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.348
-2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.348
-2 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.348
-3 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 1.012 0.516
-3 Max Skew Slow GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.546 0.516
-3 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.854 0.516
-3 Max Skew Slow GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.559 0.516
-3 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK2 GTHE3_CHANNEL/RXUSRCLK 0.882 0.348
-3 Max Skew Fast GTHE3_CHANNEL/RXUSRCLK GTHE3_CHANNEL/RXUSRCLK2 0.519 0.348
-3 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK2 GTHE3_CHANNEL/TXUSRCLK 0.914 0.348
-3 Max Skew Fast GTHE3_CHANNEL/TXUSRCLK GTHE3_CHANNEL/TXUSRCLK2 0.520 0.348
AR# 64047
Date Created 03/25/2015
Last Updated 01/12/2016
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.1