UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64049

Vivado Synthesis - Register is not absorbed into block RAM when its reset value or initial value is non-zero

Description

Xilinx block RAMs support an extra register after the RAM.

To access these, the RTL needs to be written so that the register is after the BRAM.

For example :

        always@(posedge clk) begin
           ram_out <= ram[addra];
           dout <= ram_out;
        end

However, in the following cases, the output register in the block RAM will not be used and the Slice register will be used instead.

1. If the register was declared with a non-zero initial value:

      reg [3:0] dout = 4'b0011;

2. If the register had a non-zero reset value:

      always @(posedge clka)
        if (rst)
          dout  <= 4'b0011;
        else
          dout <= ram_out;


Solution

If the register has non-zero initial value or reset value, it will not get absorbed into BRAM.

As a work-around, initialize and reset the register with zeros to have the register be absorbed into the BRAM.

AR# 64049
Date Created 03/25/2015
Last Updated 09/23/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1