Restrictions on Mixed Language in Simulation
- A VHDL design can instantiate Verilog/System Verilog (SV) modules and a Verilog/SV design can instantiate VHDL components.
Component instantiation-based default binding is used for binding a Verilog/SV module to a VHDL component.
Specifically, configuration specification and direct instantiation are not supported for a Verilog/SV module instantiated inside a VHDL component.
Any other kind of mixed use of VHDL and Verilog, such as VHDL process calling a Verilog function, is not supported.
- A subset of VHDL types, generics, and ports are allowed on the boundary to a Verilog/SV module.
Similarly, a subset of Verilog/SV types, parameters and ports are allowed on the boundary to VHDL components.
The supported data types can be found in (UG900) Vivado Design Suite User Guide: Logic Simulation.
: Connecting an entire VHDL record object to a Verilog object is unsupported.
However, VHDL record elements of a supported type can be connected to a compatible Verilog port.
- A Verilog/SV hierarchical reference cannot refer to a VHDL unit, nor can a VHDL expanded or selected name refer to a Verilog/SV unit.
However, Verilog/SV units can traverse through an intermediate VHDL instance to go into another Verilog/SV unit using a Verilog hierarchical reference.
Binding and Searching rules
When you instantiate a VHDL component in a Verilog/SV module or a Verilog/SV module in a VHDL architecture, the xelab command does the following:
- First searches for a unit of the same language as that of the instantiating design unit.
- If a unit of the same language is not found, xelab searches for a cross-language design unit in the libraries specified by the -L option.
The search order is the same as the order of appearance of libraries on the xelab command line.
Note: When using the Vivado IDE, the library search order is specified automatically.
No user intervention is necessary or possible.
Instantiation of Mixed Language Components
Instantiating a Verilog Module in a VHDL Design Unit:
- Declare a VHDL component with the same name and in the same case as the Verilog module that you want to instantiate.
- Use named or positional association to instantiate the Verilog module.
Instantiating a VHDL Component in a Verilog/SV Design Unit:
To instantiate a VHDL component in a Verilog/SV design unit, instantiate the VHDL component as if it were a Verilog/SV module.
To ensure that you are correctly matching port types, review the Port Mapping and Supported Port Types tables in (UG900) Vivado Design Suite User Guide: Logic Simulation.