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AR# 64071

UltraScale/UltraScale+ Memory IP - Custom Memory Parts Fail Simulation


Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

Simulations will fail for UltraScale/UltraScale+ memory IP example designs when using a custom created memory part.

While Xilinx does not support simulations with memory controllers targeting custom parts, some customers have experienced this behavior and rectified it with the following action.


This is due to the provided *.do simulation scripts located in the ./sim_1/imports/tb/ directory not pointing to the updated location, for example_tb.sv and example_top.sv.

To resolve the issue, run the simulation through Vivado or modify each *.do script to point to the correct location of the files.

For example:

example_tb.sv is no longer in    ../../../sources_1/imports/mig_0/tb/.

Instead it is in ../../../sources_1/imports/custom_part/custom_part.srcs/sources_1/ip/mig_0/tb/.


Similarly, example_top.sv is no longer in ../../../sources_1/imports/mig_0/rtl/ip_top/.

Instead it is in ../../../sources_1/imports/custom_part/custom_part.srcs/sources_1/ip/mig_0/rtl/ip_top/.

Revision History:

04/15/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
63462 UltraScale/UltraScale+ Memory IP - Sample CSV data file for creating Custom Parts N/A N/A
AR# 64071
Date 01/17/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite
  • Vivado Design Suite - 2015.1
  • MIG UltraScale
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