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AR# 64081

Using Vivado Simulation Libraries - SECUREIP Library


When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation.

The Xilinx libraries are divided into categories based on the function of the model.

You must specify different simulation libraries according to the simulation points.

This article describe the SECUREIP library in more detail.


The SECUREIP library is used for behavioral, functional and timing simulation of complex device components, such as Gigabit Transceiver or PCIe.

Xilinx leverages the encryption methodology as specified in the IEEE standard Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) (IEEE-STD-P1735).

The library compilation process automatically handles encryption.
To use the SECUREIP library in a third party simulator, you must have a mixed-language license or an additional licensing feature for SECUREIP if you are a VHDL user only.

Contact the simulator vendor for more information.

Note: Secure IP Blocks are fully supported in the Vivado simulator without an additional setup. 

The UNISIM library contains the wrappers for VHDL SECUREIP.

Place the following two lines at the beginning of each file so that the simulator can bind to the entity:
Library UNISIM;
use UNISIM.vcomponents.all;

Verilog SECUREIP Library
When running a simulation using Verilog code, you must reference the SECUREIP library for most simulators.
If you use the precompiled libraries, use the correct directive to point to the precompiled libraries.

The following is an example for the Vivado simulator:

-L secureip

You can use the Verilog SECUREIP library at compile time by using -f switch.

The file list is available in the file<Vivado_Install_Dir>/data/secureip/secureip_cell.list.f.
AR# 64081
Date Created 03/28/2015
Last Updated 04/15/2015
Status Active
Type General Article
  • Vivado Design Suite