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AR# 64090

Aurora Design Assistant - IPI flow

Description

The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, Initialization failures, and data errors.

The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.

Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).

The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.

Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.

Solution

 

  • Please ensure that the following ports are driven from the design_wrapper module of the block design.
    This is a mandatory requirement and independent of any core option.

    From the 2015.1 release on, CC logic has been made part of the IP.
    • CC logic ports
      • DO_CC
      • WARN_CC - for Aurora 8B10B
  • If "Shared logic in example" is selected during core generation, note the following guidelines:

    • The clocks (Example: user_clk, sync_clk) and reset input ports can be driven from a core with "Shared logic in core" option selected during generation.
      The snapshot below (from the product guide) shows the recommended connection diagram. 
Aurora 64B66B:
  •  

  •  



Aurora 8B10B:



  • If "Shared logic in core" is selected during core generation, note the following guidelines:
    • The reset (Aurora 8B10B)/reset_pb(Aurora 64B66B) input needs to be synchronized to user_clk domain.
      proc_sys_reset block can be used for synchronization of this signal if required.
      From the 2015.1 release on , this input has been made an asynchronous input to the core.

    • GT_DIFF_REFCLK and INIT_DIFF_CLK are expected to be differential input as the required differential buffers are part of the core.
       
  • If a clock input to the core is converted as a top level port of the block design, you must manually update the frequency of the clock port to match the frequency set for the core.
  • With an Aurora 64B66B core, the sys_reset_out signal should connect to the reset input of the core.
    reset_pb input is the actual reset input to the core.
  •  
    • user_clk, sync_clk can also be driven from a MMCM with txoutclk as input.
      Please ensure the MMCM is correctly configured to generate the correct frequency required for user_clk and sync_clk.

    • drp_clk, init_clk can also be driven in a similar manner from an MMCM.
      Please note that pma_init input must be asserted HIGH until init_clk is stable.

    • Also, IBUFDS_GTE[2/3] can be instantiated at the design_wrapper level and the output of this buffer can be connected to the core in block design.

      Please follow the steps below to do this.
      • Make refclk1_in/gt_refclk1 a port in the block design and create a design wrapper for the block design
      • Instantiate IBUFDS_GTE[2/3] in the design wrapper and connect the output of this buffer to the port created in the step above.
    • Similarly, QPLL can be instantiated at design_wrapper level and the input/output ports of this module can be connected to the core in block design.

      Please follow the steps below to do this:
      • Make QPLL related signal ports in the block design and create a design wrapper for the block design.
      • Instantiate QPLL in thr design wrapper and connect the input/output ports of QPLL to the ports created from the block design in the step above.
    • The reset (Aurora 8B10B)/reset_pb(Aurora 64B66B) input needs to be synchronized to user_clk domain.
      proc_sys_reset block can be used for synchronization of this signal if required.
      From the 2015.1 release on, this input has been made an asynchronous input to the core.

 

From the 2015.1 Vivado release on, the following enhancements in the core will help IPI based designs:

  •  
    • Both the reset (Aurora 8B10B)/reset_pb(Aurora 64B66B) and pma_init inputs are made asynchronous inputs.

    • When the "Shared logic in core" option is selected, the GUI provides the option to convert GT_DIFF_REFCLK and INIT_DIFF_CLK to single ended input.
      This helps when GT_DIFF_REFCLK is driven from a different core with the "Shared logic in core" option selected and targeting the same GT quad.
      Also, INIT_CLK can be driven from a MMCM.
    • The Core will automatically propagate the frequency property of "clock inputs to the core" when they are made ports in the block design.
    • With Aurora 64B66B, the reset port is removed at the core interface level and the connection from sys_reset_out to reset input is taken care of internal to the core.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61912 Aurora Solution Center - Design Assistant N/A N/A
AR# 64090
Date Created 03/29/2015
Last Updated 07/02/2015
Status Active
Type General Article
IP
  • Aurora 64B/66B
  • Aurora 8B/10B